1. Field of the Invention
This invention relates to a MOS transistor with a high-K spacer designed for ultra-large-scale integration, and, more particularly, to a MOS transistor having shallow source/drain extension regions to minimize short-channel effects.
2. Description of Related Art
Attempts continue to shrink the dimensions of MOS transistors. Devices having sub-micrometer dimensions permit closer placement of devices thereby increasing the density of devices on a chip and their operating speed.
As the size of MOS transistors decreases, the distance between the source and drain wells of a transistor, i.e., channel length, also decreases thereby subjecting the transistor to what is called "the short-channel effect." As the effective channel length of a transistor shrinks below about 0.10 micron, electrical effects begin to reduce the threshold voltage and increase leakage current of the device which eventually make the transducer useless.
One approach to minimizing the short-channel effect has been to make the depth of the channel between the source and drain shallow relative to its length. Generally this is done in one of two ways. One way is to raise the source and drain above the surface of the silicon substrate. Another way is to create extensions of the source and drain wells that are shallower in depth than the source and drain wells. These shallow extensions allow the formation of a channel between the extensions that is shallower than would otherwise occur. One way to create shallower drain and source extensions is by ion implantation.
Creating shallow drain and source extension regions by ion implantation is very difficult. At conventional implantation energy, those ions are driven deep into the silicon thereby forming a deep channel. If the implantation energy is reduced to keep the implant shallow, the individual ions' electrical fields repel one another thereby scattering and diffusing the implant which is undesirable.
Another approach has been to use cluster ion-beam implantation. At the Kyoto University in Japan, it was reported that a beam of B.sub.10 H.sub.14 ions were implanted at 2 KeV with a dose of 10.sup.12 ions/cm.sup.2. It was reported that by using cluster ion-beam implantation, a shallower channel resulted. It was reported that cluster ion-implantation created a functioning p-channel MOS transistor with a 40 nanometer gate, however, the device showed some threshold degradation as a result of the short-channel effect. A 50 nanometer transistor was reportedly built using the same technique and exhibited reportedly good gain and 0.4 mA/micron current.
In order to minimize or eliminate short-channel effects of devices created for ultra-large-scale-integration, it is desirable to provide a MOS transistor having the depth of the channel region shallower than 40 nanometer.
It is thus desirable to provide a transistor that provides acceptable immunity to short-channel effects that can be utilized in ultra-large-scale integration. It is also desirable to provide a method for fabricating such a transistor. Furthermore, it is desirable to provide a transistor that has a source/drain extension depth of less than 40 nanometers.